[반도체공정] 미래 리소그래피(lithography) 동향(영문)
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The chip makers are still using a 193 nm lithography tool with an immersion technology. However, the next-generation lithography tool is still not available and they have to continue the scaling of the devices. Therefore, this essay aims to know about trend of the future lithography and requirement of that, and also know about the double patterning, Spacer patterning which are currently spotlighted.
Contents
The general future trend of the lithography and technical requirements
Lithography technology
Photo resist (materials, sensitivities)
Optical mask
Double patterning
EUV mask
Imprint template
Conclusion (>16nm, <16nm)
DOUBLE PATTERNING/SPACER TECHNOLOGY
Step-by-step detailed procedures
Double exposure
Double Expose, Double Patterning
Spacer patterning
Necessity and Process of Hardmask for minute patterning
Material/process requirements for the hardmasks
Advantages/disadvantages of each technique
Pitch-splitting double-patterning
Spacer patterning
- 본문내용
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(4) Double patterning
The double patterning is divided into four parts, leading with wafer requirements and then two sets of lithographic requirements (Generic Pitch Splitting - Double Patterning Requirements Driven by MPU metal Half-Pitch and Generic Spacer Patterning Requirements - Driven by Flash). The lithography requirements are different for each process; the requirements for pitch splitting are based on the MPU metal half-pitch. The fundamental premise is that both the line and the space must meet the 12% CD specification. Since the space depends on the overlay and printed line width, meeting the 12% specification drives the overlay specification for double pattering. Further, to make the overlay specification as large as possible, the line width needs to be controlled to the tightest possible. In the tables, this means the double patterning line width must be controlled to the specification that an MPU gate line width would be controlled to. The mask specifications needed to support this specification are shown in the bottom rows. The matched double patterning mask image placement must be tighter than a single mask overlay by the square root of 2. Therefore, the mask-to-mask overlay contribution in any particular location must be 20% of the total pitch splitting error budget. The wafer CD error budgets for spacer patterning are also driven by the need to have both the line and space w
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